1. Field of the Invention
The present invention relates to a clock switch circuit and a clock switch method of the same, and more particularly, to a clock switch circuit and a clock switch method of the same that switch a plurality of frequency-divided clocks obtained by dividing a frequency of a basic clock according to a clock select signal.
2. Description of Related Art
In recent years, the speed of the operation frequency has been significantly increased in a field of a system LSI (Large Scale Integration circuit), and especially in a field of a system LSI mounted on a mobile device. There is an increasing demand of low power consumption in the system LSI used for such an application. In the system LSI, low power consumption is realized by switching clock frequencies according to the operation state. It is required to dynamically switch clocks from high frequency to low frequency while keeping the pulse width before and after switching of clock frequencies to ensure the normal system operation.
One example of the clock switch circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2008-123402. Japanese Unexamined Patent Application Publication No. 2008-123402 discloses a variable clock generation circuit corresponding to the clock switch circuit. The variable clock generation circuit includes a frequency dividing decoder and a next state storage flip-flop. The frequency dividing decoder 11 receives a state (S5) and a frequency select signal (S3), and decodes the state (S5) based on S3 and S5 to generate a next state (S6). The next state storage flip-flop latches the next state (S6) by an input clock (S1) to generate the new state (S5). The frequency dividing decoder 11 and the next state storage flip-flop constitute a sequential circuit having a plurality of states (S5). The next state storage flip-flop outputs one bit of the new state (S5) that is generated by latching the next state (S6) as a frequency-divided clock (S4).
Further, in the variable clock generation circuit, the frequency dividing decoder includes a plurality of divided state decoding units corresponding to the plurality of divided frequencies. In the frequency dividing decoder, a plurality of divided state decoding units are used by being switched based on the frequency select signal, so as to switch the frequency of the frequency-divided clock that is to be output. Thus, in the variable clock generation circuit, the frequency-divided clock having a given divided frequency can be output. Further, the frequency dividing decoder includes an idle state decode unit, and outputs the output of the idle state decode unit as the next state (S6) in switching the frequency-divided clock that is to be output, so as to prevent a glitch that is produced in switching the divided frequency of the frequency-divided clock. The symbols shown in parentheses in the above description correspond to those shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2008-123402.